This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
At higher core voltages, write failures may occur due to false read when timing mismatch takes place between row and column select lines, even at skewed corners (e.g., when a core voltage VDDC is much larger than a periphery voltage VDDP. For instance, during a write operation, if a wordline signal arrives before a write driver signal, then both the bitline and the complementary bitline may be pulled down to ground (GND), thereby likely inhibiting a write operation on an associated memory bitcell. Also, for pseudo-dual port designs, where the write operation is followed by a read operation in a same cycle, a much higher discharged bitline during read operation may cause the above issue if it is not precharged back before the write operation starts, even if VDDCE=VDDPE. Further, precharging the bitlines back to VDD before the write operation may start impacting the read/write cycle time. In dual port SRAM, the cycle time may be impacted even at the same core voltage and periphery voltage, where simultaneous access is made on a same row but a different column. In this case, when performing a first port A write operation “0” (i.e., writing cored=0 from 1), and/or when performing a second port B dummy read operation, a voltage drop on the read bitline may limit the port B bitline from rising, thus likely causing a write failure to take place. As such, there exists a need to improve circuit designs to reduce possibility and occurrence of false reads.